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? motorola, inc., 1997 an1712 order this document by an1712/d motorola semiconductor application note an1712 "get your motor running" with the MC68HC708MP16 by david wilson motorola field applications engineer milwaukee, wisconsin introduction the quality of life we enjoy today can easily be correlated to the existence of the electric motor. indeed, many of the products in our homes either have motors in them or a motor was used to manufacture them. for instance, we counted 114 motors in our house alone, not including our cars or the kids' toys. however, the plethora of these electro-mechanical marvels in our society constitutes an insatiable appetite for electrical energy. according to the u.s. department of energy, 58% of the electricity generated in the united states is consumed by electric motors [1] , and no relief is in sight. with a focus on energy consumption and environmental issues, companies are scrambling for ways to put these motors on a "diet." one solution which is becoming more and more palatable is electronic control. if motor energy consumption continues along present trends, the crucial question in the near future will not be "can we afford electronic control," but rather, "can we afford not to have electronic control." the explosive growth of power semiconductors and processor technology within the last decade has made electronic control of all motor types more economically feasible. microcontrollers in particular have enjoyed a recent upsurge in popularity for motor control
application note an1712 2 motorola applications. as more control loops are implemented digitally, control techniques which would have been difficult or impossible with analog circuitry (such as adaptive control) are becoming commonplace. smarter fault management, variable frequency waveform generation, and communications with other systems are all benefits brought to the motor control arena by the microcontroller. also, feature enhancements on motor drives in production can often be handled by software upgrades without having to "rev" the board layout. in fact, one manufacturer of motor drives cleverly manages its inventory by building a hardware unit which is used across several drive products. different control software running on this common hardware platform distinguishes one product from another. once the decision has been made to use a microcontroller in a motor control system, the engineer is faced with the formidable task of selecting which one is best suited for the job. in many cases, for instance, the cpu may be ideally suited for the particular motion control task, but important features are missing in the embedded peripherals, forcing the designer to add more hardware to compensate for the deficiency. or perhaps the peripherals are just right for the application, but the cpu is oversized or lacking in development support. in many cases, the designer settles on a dsp (digital signal processing) solution, only to find that it executes the digital filters with time to spare, but is difficult to program for the rest of the routines. in fact, many engineers have related that more than 90% of their motor control code is "non- dsp" related, and that the cpus data management features can be more important than its dsp features. if you have struggled with any or all of these issues, then please read on. engineers at motorola have "come together, right now" to address these concerns with the new MC68HC708MP16, which can get just about any motor running (unless it runs on gasoline, in which case you're reading the wrong paper). the 'mp16 has been specifically designed to meet the requirements for low-cost dc servo and ac "open loop" systems (see figure 1 ).
application note introduction an1712 motorola 3 figure 1. hc08mp16 block diagram anyone who has worked with the popular hc05 family of microcontrollers will appreciate the rich enhancements to the instruction set provided by the cpu08 while at the same time maintaining object code compatibility with its hc05 parent. other enhancements such as a 16-bit index register and stack pointer, 5-cycle multiply instruction, and high-level language support (c language) make the cpu08 ideally suited for most motion control applications. another distinguishing feature of the 'mp16 is its powerful pwm generator module, which can be configured and partitioned in a variety of ways for different motor control applications. figure 2 offers a more detailed view of this module, which will serve as the focus for much of this application note. pwm 1 pwm 4 pwm 2 pwm 3 pwm 5 pwm 6 cpu 08 sim cgm 16k rom/eprom 512 bytes ram 8 bit a/d converter pwm generator spi sci tim4 fault inputs 10 4 irq1 2 general purpose i/o 13 reset 64-pin qfp 5 current polarity pins lvi 3 tim2
application note an1712 4 motorola figure 2. pwm module block diagram up/down counter trigger pwm3 pwm4 pwm5 pwm6 system faults interrupts or prescaler bus clock ? 1, 2, 4, or 8 fault protection prescaler ? 1, 2, 4, or 8 pwm reload and interrupt motor current polarities pwm generators comparators double pwm mode fault partitioning fault mode select high polarity control distortion correction dead-time insertion direct output control select output control buffered registers current drivers pwm1 pwm2
application note pwms designed for your system, not vice versa an1712 motorola 5 pwms designed for your system, not vice versa as alluded to earlier, a leading cause of frustration and consternation for motor control design engineers is finding that the pulse width modulator (pwm) requirements needed for the motor drive are incompatible with the pwm capabilities of the selected microcontroller. as a result, you're left with this big hole in the middle of your schematic that needs to be filled with an assortment of gates and glue and buffers and so on. the 'mp16 was designed from a system point of view in an effort to minimize as many of these incompatibilities as possible, while keeping the cost for this flexibility low. after analyzing many of our customer's different motor control applications, motorola soon discovered that a large number of them had similar requirements which could be addressed by enhancing the flexibility of the pwm module. some of the 'mp16 features that account for this flexibility are discussed next. living on the edge or in the center the 'mp16 can generate one of two types of pwm signals from the pwm module at any given time from the pwm module edge-aligned or center-aligned determined by the state of the edge bit in the config register. figure 3 shows both waveform types where the vertical line represents a waveform alignment reference. the counter value (represented by the bold traces) is shown being digitally compared against two levels which are determined by the pwm value registers, and represent desired pulse widths. the pwm signals shown are the result of those comparisons. to prevent erroneous pulse widths while the software is loading new pulse width information, the pwm value registers are all double buffered. this information is picked up by the pwm generator at the beginning of every one, two, four, or eight pwm cycles, determined by how software loads the ldfq0 and ldfq1 bits in pwm control register 2.
application note an1712 6 motorola figure 3. pwm waveform types the counter in the pwm module counts from $000 hex to the value specified in the pwm counter modulo register (up to $fff maximum), where each counter "tick" can be as fine as 125 ns for an 8-mhz bus. the pwm x value registers each hold a 16-bit value partitioned as an upper byte and lower byte. as long as bit 15 of this value is clear (indicating a positive number), the number is compared to the counter value to generate the desired pulse width. any value greater than or equal to the counter modulus will result in a pwm signal with a full 100% duty cycle. however, if bit 15 is set (indicating a negative number), the value will instead be treated as 0, resulting in a duty cycle of 0%. that's right. zero. zip. nada! this automatic "saturation mode" of operation permits overmodulation of the motor waveform which might result from small finite word length errors, guaranteeing rail-to-rail operation without having to deal with modulo wraparound at 0. otherwise, the software would have to check each pwm value and branch if it was less than 0 to load a 0 value instead. this mode of operation can be compared to the way an op-amp output works when you overdrive its input. it just saturates instead of driving to the other rail. edge aligned center aligned alignment reference modulus = 16 modulus = 8
application note together, or not together . . . that is the option an1712 motorola 7 from an inspection of figure 3 , it may be difficult to see why one pwm waveform is preferred over another in a motor control application. if you're looking for the best resolution possible at a given pwm frequency, consider using edge-aligned mode. figure 3 shows that for the same pwm waveform period, edge-aligned operation allows the counter modulus to be twice as high as that of center-aligned mode, thereby doubling the pwm resolution. however, for most motor control power stages that use multiple half bridge transistor arrangements, the benefits resulting from the interaction between center-aligned pwms justify their selection. more on this later. together, or not together . . . that is the option the 'mp16 pwm module can generate up to six independent pwm signals, all synchronized to the same counter/timer. if that isn't enough, three additional pwm signals can be obtained from the timer modules, two of which are synchronized to a separate time base, and the third synchronized to still another time base. in other words, a total of nine independent pwm signals are possible from the 'mp16, running at up to three different pwm frequencies. figure 4 shows the familiar igbt half bridge used with many motor drives. in some instances, it is desirable to control these devices in a complementary fashion such that when one device is on, the other is off, and vice versa. however, if power is applied across the half bridge, you never want to have both transistors on at the same time, since fire, smoke, and other unpleasantries may result. to drive the transistors in a complementary fashion, the 'mp16 provides a separate operating mode specifically for this purpose. by setting the indep bit in the config register to 0, the six pwm signals are configured as three pairs of complementary pwms. this is extremely useful when controlling a 3-phase power module, such as the versapower module available from motorola and shown in figure 5 .
application note an1712 8 motorola figure 4. igbt half-bridge circuit incidentally, the versapower module comes in several different package configurations such as the 24-pin package shown, which houses the off- line input rectifiers, six inverter igbts, a brake transistor, and a temperature sensor. a 16-pin package containing just the output power section is also available. one, two, and three horsepower devices are planned. it is not sufficient for the bottom igbt pwm signals to simply be inverted versions of the top igbt pwm signals. due to delay uncertainties in the igbts and the supporting circuitry, it is necessary to have a "dead-time" inserted between the turn-off of a given igbt and the turn-on of its complementary device to guarantee no overlapping "on" times. the 'mp16 provides this dead-time insertion automatically with each pwm transition in complementary mode, thus eliminating the need for external timing circuitry. the dead-time for all pwm signals is specified as a single 8-bit value representing the number of cpu clock cycles per dead-time interval. for an 8-mhz bus, this implies a dead-time range from 125 ns to more than 30 m s. for igbt motor drives under 10 hp, typical dead-time values range anywhere between 2 m s to 10 m s. i + i 1 C v + v C
application note together, or not together . . . that is the option an1712 motorola 9 figure 5. complete 3-phase integrated power module from motorola d5 d6 6 5 9 10 11 12 20 19 16 15 2 14 13 17 24 23 18 18 7 r ntc u v w r s t 3 phase input motor 34 22 21 brake resistor c1 + temp sense d14 r1 q5 q6 d1 d2 q1 q2 d3 d4 q3 q4 d8 d9 d10 d11 d12 d13 q7 d7 filter sense resistor 3.90 4.39 2.02 output
application note an1712 10 motorola do it with more power! having opto-isolators in the pwm signal path is common, especially for the high-side transistors. the chosen opto should be fast and have a high enough common mode dv/dt rating to prevent noise from appearing on the pwm signals. one such opto that is well suited for high-voltage motor drive pwm applications is the hcpl-0453. like many other optos, high light-emitting diode (led) currents (approximately 15 to 20 ma) are often required to achieve optimal performance, depending on the circuitry connected to the opto's output. the 20-ma current sink capability of the 'mp16 was designed with this requirement in mind. figure 6 illustrates an optically isolated high-side gate driver circuit utilizing the 'mp16 to drive the opto-isolator directly. figure 6. pwm buffer circuit using an opto-isolator hcpl0453 fault input v ee gnd sense output desat mc33153 v cc +18 v +5 v pwm1 gate emitter 2.2 180 10 m f 0.1 m f 5.6 k 100 22 hc08mp16 pwm2 pwm3
application note high or low pwm outputs: whatever turns you on an1712 motorola 11 high or low pwm outputs: whatever turns you on by the time the pwm signal makes its journey through the optos and gate drivers, it may arrive at the power device with the wrong polarity. this can really be annoying, especially if extra hardware is required just to invert the pwm signals. with the 'mp16, the polarity can be specified for the odd numbered pwm signals independently from the even pwms. it is assumed that the odd numbered pwms will be used to control the top transistors in a drive, and the even numbered pwm signals will control the bottom transistors. the bits topneg and botneg in the config register allow the software to invert the top and bottom pwm polarities respectively. this is also useful when interfacing a new microcontroller board to an existing power stage with established pwm polarity requirements. when the 'mp16 is first powered up or reset, the pwmen bit in the pctl1 register is 0, and the pwm pins assume a high-impedance state. if an opto is driven directly from a pwm output, a polarity convention, therefore, should be established where no led current corresponds to the "off" condition. during this high-impedance time, the software must program the correct polarity information into the config register before enabling the pwms by setting the pwmen bit. once this bit is set, all pwm outputs will exit the high-impedance state and be negated for one cpu clock cycle before being driven in accordance with the values programmed in the pwm module. from that point on, if the processor shuts down the pwms for any reason, they will be quickly driven to the "off" voltage level instead of floating, since the processor now knows which voltage level is "off."
application note an1712 12 motorola development tool compatibility when using the development equipment with some motor control micros, extreme care must be taken or damage may result to the motor and the drive under development. for example, when a break point is encountered in the code stream, some micros just leave the pwms on with their present pulse width, or worse, freeze the pwms in their present states. for many motor types (including ac induction motors), either of these conditions causes the motor to stop abruptly, resulting in potential damage to the motor drive. the 'mp16 was designed to take emulation tool support into consideration by negating all of the pwms (driving them hard off) under break conditions. this disables the power stage, resulting in the motor coasting safely to a stop. whose fault is it? most motor drives on the market today have earned a reputation for being robust and "bulletproof" thanks in large part to their fault tolerance. sensing of such parameters as bus voltage, heat sink temperature, and over-current conditions as means of protection are becoming more and more commonplace. signals representing these parameters are often supplied to an analog-to-digital (a/d) converter and then regulated by software. however, if corrective action is required immediately, software alone is often inadequate to provide the necessary protection. for this reason, such system parameter signals are often compared in hardware against a threshold that represents an unacceptable level, and fault signals are created to disable the drive immediately. therefore, the drive's microcontroller should have the capability to process these signals, and immediately disable the pwm outputs when a fault condition is present. however, most microcontrollers on the market today can accommodate only one fault signal, requiring the hardware designer to include extra circuitry just to gate all the fault signals together. it is left up to the software engineer to figure out which signal is responsible for the fault.
application note whose fault is it? an1712 motorola 13 it is even more frustrating if the offending fault has disappeared by the time the software responds. this may not foster feelings of harmony and good will between the software and hardware engineers. to simplify the hardware design task, the 'mp16 has four fault inputs that are connected directly to the pwm module to immediately disable its outputs. these inputs are evenly split into two banks that can be programmed to disable different pwm outputs. this allows the 'mp16 to control up to two independent power stages, each with their own fault feedback signals. examples of this are presented later. the software engineer will appreciate the fact that each fault input has its own interrupt vector, allowing a separate interrupt service routine to be executed for each fault condition without having to poll separate input/output (i/o) inputs to determine what caused the fault. in addition, the cpu is capable of reading the immediate status of the fault inputs via the fpinx bits in the fault status register (fsr). all fault inputs work identically in terms of how they disable the pwm outputs. when a fault occurs, the corresponding pwm outputs are disabled immediately. when and how they become enabled again is dependent on which operating mode is in effect for that fault input. each input can be programmed to work in either manual mode or automatic mode, both of which are described in this application note. take control in manual mode in manual mode, the software is responsible for reactivating the pwm outputs. however, when this mode is selected, the odd numbered fault inputs work differently than the even numbered inputs. for an odd numbered fault, the affected pwms will be reactivated on the next pwm cycle after the software has acknowledged the fault by clearing the associated ftack bit in the ftack register. the software assumes full responsibility for pwm enabling, and the pwms will come back on line even if the fault is still asserted. this is useful for processing faults that may have a long time constant or hysteresis associated with them, but the pwm outputs are still required to be active during the time it takes the fault signal to negate.
application note an1712 14 motorola the even numbered fault pins work almost the same way except that the pwms will be enabled on the next pwm cycle after the software has acknowledged the fault and the fault signal is negated. this provides ultimate protection, even for the condition where the ftack bit may have been accidentally cleared (for instance, runaway code). another application would be when the software has granted pwm enabling by clearing the ftack bit, but in the meantime wants the pwms to remain disabled until the fault input is negated. at that point, the pwms will come back on line automatically. an easy way to remember the difference between the odd and even fault pins is to think that the even pins provide even more protection. take it to the limit in automatic mode automatic mode is a unique operating mode where the pwm outputs can be turned back on automatically at the start of the next pwm cycle, assuming that the offending fault has gone away. the primary application for this mode of operation is cycle-by-cycle current limiting, as illustrated in figure 7 . a resistor inserted in series with the motor develops a voltage when current is flowing through the motor. this voltage is compared to a threshold representing a safe upper current limit, and the comparator output constitutes the fault input signal. the dashed portion of the pwm waveform indicates the normal duty cycle that would have occurred without current feedback. the solid line shows early termination of the pwm signal's "on" time resulting from the current threshold being reached. cycle-by-cycle current limiting allows the motor current to be regulated automatically by the protection hardware of the 'mp16, thus freeing the software to focus on other control tasks.
application note whose fault is it? an1712 motorola 15 figure 7. cycle-by-cycle current limiting + - from amplifier motor current safe threshold to mp16 fault input programmed for automatic mode safe threshold motor current fault signal pwm
application note an1712 16 motorola you can bank on it as was mentioned earlier, the four fault inputs are segregated into two separate banks. fault inputs 1 and 2 are combined with software bit disx in the pctl1 register to constitute the disable for bank x, while inputs 3 and 4 are combined with the disy bit in the pctl1 register to create the disable for bank y. these signals are then presented to the disable mapping logic shown in figure 8 , which allows each disable signal to negate some or all of the pwm outputs. figure 8. pwm disable mapping logic bank x bank y disable pwm1 disable pwm2 disable pwm3 disable pwm4 disable pwm5 disable pwm6 bit 1 bit 2 bit 3 bit 4 bit 0 bit 5 bit 6 bit 7 dismap $0037 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
application note whose fault is it? an1712 motorola 17 to illustrate how the disable mapping logic can be used, refer again to figure 5 and figure 6 . with drives that contain high-side gate driver circuits as shown in figure 6 , it is sometimes useful to pwm the lower transistors while the upper transistors remain disabled at initialization time to charge pump the gate drive power supply capacitor. this may be accomplished by programming $b6 in the dismap register, which allows bank x to disable all the transistors while bank y disables only the upper transistors (assuming that the odd numbered pwm outputs are used to drive the upper transistors). configured as such, any fault conditions that would require shutdown of all pwm outputs would use fault pins 1 or 2, since they are channeled into bank x. by specifying the state of the disy bit in the pctl1 register, the software can selectively enable and disable the upper transistors without affecting the lower transistors. the fault partitioning scheme also is useful when the 'mp16 is called upon to control two separate power stages simultaneously, such as a converter/inverter combination, or two dc motor h-bridges. an example of this is included in this application note.
application note an1712 18 motorola be direct on occasion, software may need direct control over the pwm outputs. for example, when the drive is first powered up or reset, software may perform drive diagnostics where each power device is controlled individually. in such instances, the user will find the pwm output control port to be a useful feature on the 'mp16. by setting the outctl bit in the pwmout register, the pwm generator is disconnected from the output pins, even though it continues to run. pwm outputs are then controlled directly by bits out1Cout6 in the pwmout register. however, unlike ordinary i/o ports, the pwm output control port provides two protection features for the drive hardware: ? dead-time is still active for complementary outputs if complementary mode is enabled. for example, there is no way to have both pwm1 and pwm2 active at the same time nor to have the dead-time between the assertion of one and the negation of the other to be violated. ? the outx bits do not control the actual voltage level at the pwm pins; only whether they are asserted or negated. the polarity convention established by the toppol and botpol bits is still in effect. again, the thinking is to prevent accidental damage to the drive hardware in the event of runaway code (or a temporary moment of insanity exhibited by the software engineer). a table showing output performance for outx bit conditions is located in the user's manual for both complementary and independent modes of operation.
application note it takes a licking . . . keeps on ticking an1712 motorola 19 it takes a licking . . . keeps on ticking since the processor's oscillator circuit literally is the heartbeat of the entire system, care must be taken to ensure that it is functioning properly at all times. as of the time of this writing, at least one european regulatory agency is considering a dead-oscillator test on a running machine to observe the failure mode. the clock generation module (cgm) on the hc08 family has been specifically designed to withstand the rugged requirements of industrial applications. to this end, a phase-locked-loop (pll) has been implemented in the silicon, which yields a twofold advantage for industrial applications: 1. the clocking circuit is much more immune to noise spikes on the crystal input. this is an important feature when considering that in many motor drives, the processor is located very close to the power switching devices. with the 'mp16, any noise spike on the crystal input pin will be interpreted as a change of the input frequency by the pll, which will slowly adjust its output frequency in the direction of the perceived frequency change. on a processor without a phase-locked-loop, the noise spike could cause a timing violation in the cpu state sequencer, which in turn could crash the processor. 2. the pll has a special bit called the lock bit that can generate a cpu interrupt informing it if phase lock has been lost. at this point, the processor can test the crystal integrity via the crystal loss detect bit and respond gracefully to the situation, taking the appropriate actions. note also that even if the external clock input is lost completely, the pll will continue to run at a frequency of roughly one-third the vco's center-of-range frequency.
application note an1712 20 motorola load em and leave em the 'mp16 relies heavily on "write-once" registers as the cornerstone to its output protection strategy. many programmable features such as the pwm output polarities are actually fixed system parameters that should not require changing once they are specified. without such protection, if the polarities are changed inadvertently by a software bug or runaway code after being correctly loaded, the software engineer could be forced into the awkward position of having to inform the hardware engineer that his or her board has blown up. in the spirit of increasing motor drive longevity, motorola has designated as write-once registers some of these registers that could affect the protection integrity. for instance, the software may write to them only one time after each reset. these registers and their addresses are: configuration register (config) $001f dead-time register (deadtm) $0036 pwm disable mapping register (dismap) $0037 application examples despite the wide diversity of motor types available today, it may come as quite a surprise to realize that most motors work pretty much the same way. for example, torque is developed in an ac induction motor the same way it is in a dc motor. this realization led felix blaschke, a researcher at siemens, in 1968 to pioneer the concept of field orientation with induction motors [2] . even the stepper motor (which is often inappropriately described as a "digital" motor) is really an analog motor that develops torque the same way as other motors. the design of the 'mp16 pwm module capitalizes on these similarities, which allows it to control many different types of motors. a few examples illustrating this point are given here.
application note application examples an1712 motorola 21 low-cost, v/hz induction motor controller the torque produced by a common ac induction motor is shown in figure 9 as a function of motor shaft speed. a typical hvac load also is plotted for comparison. even though the induction motor is an asynchronous motor, it still tries to run at a speed close to its input frequency, as evidenced by the steep slope of the speed-torque curve at the load intersection point. as the amplitude of the voltage sine wave(s) applied to the motor decreases, the motor's speed-torque curve will be attenuated, permitting a limited range of variable speed operation. this method of speed control is very load dependent, however, and is generally not used, especially with nema type a or b motors which have a steeper speed-torque slope. the more generally accepted practice is to vary the frequency of the ac waveforms to the motor, resulting in the motor curve in figure 9 shifting either right or left depending on the direction of the speed change. since electric utilities are reluctant to change the frequency they generate, dc motors ruled supreme in variable speed applications for decades, even though ac motors are more reliable and in some cases, up to six times cheaper. but this situation has changed today with the advent of the induction motor variable speed drive (vsd), which can produce power sine waves at continuously variable frequencies. in the 'mp16, this is accomplished easily by defining a digitized sine wave figure 9. speed-torque curve for an induction motor and a typical load shaft speed torque typical load induction motor stator frequency
application note an1712 22 motorola look-up table in the processor's memory and spooling data out of this wave table to the pwm generator to create different frequency sine waves, as illustrated in figure 10 . for low-cost, open-loop applications, the input variables to the pwm routine are simply the desired voltage and frequency to be applied to the motor. the functions shown would typically exist as an interrupt service routine initiated by a periodic interrupt from the pwm module. in fact, the pwm module can be programmed to provide this interrupt at a rate of every one, two, four, or eight pwm cycles to accommodate the time required to execute the interrupt routine. to generate a 3-phase output, the data for phase one is fetched from the wave table at a location corresponding to the pointer position calculated by the integrator. a value is then added to the pointer, resulting in a shift of 120 degrees (85.33 points for a single-cycle table of 256 points), and the data for phase two is indexed. if the pointer is incremented to an figure 10. pwm generation technique 1000 1050 f q integrator sine table pointer x x x waveform table v inputs to isr pwm1 value register pwm5 value register pwm3 value register 0 50 100 150 200 250 0 200 400 600 800 C26 s4 wave ( q ) wave ( q + 2 p /3) wave ( q + 4 p /3)
application note application examples an1712 motorola 23 address beyond the end of the table, take care to ensure that the pointer wraps to the beginning of the table. this will be handled automatically by the modulo arithmetic associated with the pointer increment if the number of entries in the wave table is sized to match the pointer word length. phase three data is obtained by a further 120-degree increment of the pointer. this technique supports bidirectional motor operation by controlling the sign of the frequency variable. negative frequencies result in reverse shaft rotation, and the pointer simply is decremented by the integrator instead of incremented. again, if the wave table is sized to match the pointer wordlength, the modulo arithmetic automatically will handle the required wrap-around when the pointer is decremented beyond the beginning of the table. code has been written for the 'mp16 which executes the functions shown in figure 10 in 33 m s for an 8-mhz bus. to put this in perspective, the 'mp16 could generate 10-khz pwms for a 3-phase motor, updating all the pwm values at the start of each new pwm cycle, and still have 66% cpu bandwidth remaining for other tasks. since ac motor control is the target application of the 'mp16, one can reasonably expect that the part is ideally suited to this task. a typical hardware configuration is shown in figure 11 . the dismap register retains its default value of $ff, which allows a fault condition on any of the fault inputs to disable all the pwm outputs. all fault inputs are programmed to work in manual mode, and the current fault uses the fault2 input, which means the software must acknowledge the fault and it must go away before the pwms can be reactivated. the temperature and bus voltage faults are returned to the odd-numbered fault pins, which implies that the fault still can be asserted when software reactivates the pwms. this permits these signals to have long time constants and/or hysteresis. since each of the six inverter transistors is driven with a unique pwm signal, the full advantages of center-aligned operation can be realized. also, complementary mode should be specified and a dead-time value written to the dead-time register before the pwms are enabled.
application note an1712 24 motorola figure 11. low-cost 3-phase ac motor control system split-phase induction motor controller the split-phase induction motor is a polyphase motor with its windings spatially separated by 90 electrical degrees. by supplying quadrature current waveforms to the two windings, motor rotation is achieved with less torque ripple than that attainable with a single-phase induction motor with a start winding. this is commonly achieved by putting a large, non-polarized capacitor in series with one of the windings and powering both phases from the same single-phase supply. rotational direction is determined by which phase is connected in series with the capacitor. hc708mp16 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 bus voltage processing bus current processing temperature processing atd0 atd1 atd2 fault2 fault1 fault3 high voltage micro to motor interface u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 c1 c2 c3 c4 c10 j1 jp1 jp2 jp3 j2 r1 r2 r7 r8 r9 r11 r12 r19 r21 r23 r25 r30 r26 r29 r31 r32 u12 j3 itc132 to ac motor versa- power
application note split-phase induction motor controller an1712 motorola 25 figure 12 shows a simple power circuit that can achieve the quadrature waveforms without the capacitor in series with the motor winding. by using the 'mp16 to control the pwms to the four transistors, precise quadrature current waveforms can be created that will allow the motor to rotate in either direction at variable speeds. as can be seen, this technique results in a simpler converter/inverter power configuration than its 3-phase counterpart. the 'mp16 pwm module would be programmed for complementary operation between the odd and even numbered pwms, and the dead-time would be programmed just like the 3-phase motor control example. a software lookup table could also be used in the manner described in the last section to generate the waveforms for both phases. figure 12. variable speed, split-phase motor controller pwm1 pwm2 winding a winding b pwm3 pwm4 cos( w o t) cos( w o t p /2) squirrel cage rotor single phase ac
application note an1712 26 motorola switch reluctance motor control although the principle of switch reluctance (sr) motors has been around since 1838, only recently have they moved into the spotlight, thanks in large part to the economic benefits obtained by lower-cost electronic control. the advantages claimed by these motors are quite impressive. for example, one sr motor manufacturer is already claiming a 10% reduction in manufacturing costs compared to an induction motor of the same horsepower rating. this number is expected to improve as the manufacturing infrastructure for these motors is put in place. combined with its rugged construction (no rotor conductors or magnets) and boasts of greater efficiency and speed range, sr motors pose some interesting possibilities down the road. of course, you don't get something for nothing. and with sr motors, the price to be paid is no direct on-line capability (electronics are needed to commutate the motor.) and increased torque ripple and audible noise resulting from the doubly salient design of the rotor and stator. by using the pwms on the 'mp16, the current in each phase can be profiled and overlapped with the current in other phases to provide smoother and quieter operation. consider the configuration in figure 13 . such a circuit would control a 4-phase sr motor, the most common being the 8-stator pole, 6-rotor teeth design with a 15-degree stroke. it is interesting to note that the same circuit can provide chopper control of a 4-phase stepper motor. the 'mp16 controls which phases are energized at any given time by measuring the motor shaft position and using four of its general-purpose outputs to turn on the appropriate bottom transistors. the top transistors are controlled from the pwm generator. in this application, it is assumed that only one motor phase from a given pair will be on at a time.
application note switch reluctance motor control an1712 motorola 27 figure 13. 4-phase switch reluctance motor control power stage by programming the even numbered fault pins to operate in automatic mode, independent cycle-by-cycle current limiting is obtained for each pair of phases. for this to work, the dismap register is programmed with $00 (or any value that ensures that pwm1 is affected only by fault inputs 3 and 4, and pwm6 is affected only by faults 1 and 2). when current limiting occurs, the upper transistor associated with that pair of phases is turned off, but the bottom transistor remains on to allow smooth freewheeling of the current through either d5 or d6. current is extinguished in a given phase by turning off both the top and bottom transistors associated with that phase, forcing current commutation back through the dc supply. if a bus over-voltage occurs, all motor phases must be disabled. this implies that the voltage processing circuitry must use two fault inputs, one to disable pwm1 and one for pwm6. both of these fault inputs would be programmed to operate in manual mode. phase 1 phase 3 current phases 1/3 fault 4 fault 2 pwm 1 d5 d2 d1 gpio1 gpio3 voltage processing circuitry faults 1 & 3 comparator current comparator phases 2/4 phase 2 phase 4 pwm 6 d6 d4 d3 gpio2 gpio4
application note an1712 28 motorola since the motor phases are connected between the top and bottom transistors, dead-time insertion is not required. operating in independent mode with edge-aligned pwms would thus be a logical selection, yielding a pwm resolution of 125 ns for a bus frequency of 8 mhz. figure 14 shows typical current waveforms for a 4-phase sr motor [3] . waveshaping could once again be obtained using a waveform table as described in the application section on induction motors. to preserve processor bandwidth, the software can elect to disable current waveshaping at higher rpms in favor of a simpler "stepper" type of control scheme. figure 14. typical current waveforms of a 4-phase sr motor multiple dc motor control the pwm module in the 'mp16 has been designed to accommodate more than one power stage, as shown in the example in figure 15 . for this configuration, the dismap register would be programmed to $44 hex. since the fault logic is comprised of two separate banks, the current in each motor can be controlled independently on a cycle-by-cycle basis by programming fault inputs 2 and 4 for automatic mode. a bus over- voltage could be caused by either motor, so the voltage-sensing circuitry must be connected in such a way that an over-voltage fault disables both banks of pwms. 90 degrees phase 1 phase 2 phase 3 phase 4
application note multiple dc motor control an1712 motorola 29 figure 15. dual h-bridge motor control configuration in this example, complementary mode should be selected, and a dead- time value programmed into the dead-time register. since both sides of each h-bridge are driven by the same pair of pwm signals, there is little advantage in specifying center-aligned pwm operation, especially since edge-aligned operation yields twice the resolution for a given pwm frequency. in the next example, the benefits of center-aligned pwms are demonstrated. v bus pwm1 pwm1 pwm2 pwm2 hc708mp16 atd4 value pwm1 pwm2 pwm5 pwm6 fault1 limit value trip atd1 fault3 fault4 atd2 value limit fault2 current processing current processing motor 1 pwm5 pwm5 pwm6 pwm6 motor 2 voltage processing
application note an1712 30 motorola figure 16 shows typical pwm waveforms for this drive configuration. in preparation for the next example, notice that the motor terminal voltage swings from +bus to Cvbus at a frequency equal to the pwm frequency. figure 16. pwm waveforms resulting from edge-aligned pwms high performance servo controller this application takes full advantage of the center-aligned pwm output capability of the 'mp16. to do this, each transistor must be driven with its own unique pwm signal, as shown in figure 17 . the motor current is limited on a cycle-by-cycle basis by programming fault inputs 2 and 3 for automatic mode and driving them from comparators that monitor the current in each leg of the h-bridge. fault input 1 provides overvoltage protection during regeneration by disabling the pwms when the dc bus voltage is too high. for this example, fault input 1 would be programmed to operate in manual mode. the software must generate two pwm values: one for the left side of the h-bridge and one for the right side. if the average of both of these duty cycles is 50%, something wonderful happens as shown in figure 18 . first, the pwm frequency seen by the motor is twice that applied to each transistor. this effect alone will reduce the motor ripple current by at least 6 db, assuming the frequency is higher than the pole formed by the electrical time constant of the motor. second, the peak-to-peak voltage applied to the motor is half that of the previous example, reducing the ripple current even further. also, for the condition of near 0 volt motor operation where servo requirements are the most stringent, the motor pwm1 pwm2 motor + v bu s C v bus
application note high performance servo controller an1712 motorola 31 current is commutating effectively into a diode and a transistor drop versus the bus supply as in the last example. this has the effect of lengthening the time constant of the current commutation, which also smoothes the current waveform. as might be expected, coreless rotor designs and low-inductance motors in general stand to benefit from this type of control. figure 17. high performance dc servo control v bus pwm1 pwm4 pwm2 pwm3 hc708mp16 atd2 value pwm1 pwm2 pwm3 pwm4 fault2 channel a channel b motor limit value trip atd1 fault1 atd3 value fault3 limit tch0b tch1b tch2b tch3b filtered encoder inputs d q s r q 74hc74 20k 100 pf 10k 100 pf v cc v cc v cc 74hc86 74hc86 74hc86 74hc86 up/down encoder count clock tclka tch0a a b c d voltage processing current processing current processing ?
application note an1712 32 motorola recall that center-aligned pwm mode yields half the resolution for a given pwm frequency compared to edge-aligned mode. however, by judicious calculation of the two pwm values, this reduction in resolution can be recouped for this application. consider the "motor" waveform of figure 18 . each consecutive positive pulse has the same duty cycle since the pwm 1 and pwm 3 value registers are programmed to produce identical pulse widths. what would happen if this were not the case? for example, suppose one count is subtracted from the pwm 3 value register to produce a slightly longer positive pulse width than that of the pwm 1 value register. the effective high time over a pwm cycle (as defined by a complete up/down cycle of the pwm counter) would be the average of these two widths. in other words, the average pulse width would be in between that specified by the pwm 1 and pwm 3 value registers, yielding a 1/2 count resolution. figure 18. center-aligned pwm effect on motor pwm1 pwm2 pwm3 pwm4 motor gnd C v bus pwm frequency at motor is doubled voltage swing is halved motor ripple current is reduced pwm1 value register pwm3 value register 50%
application note high performance servo controller an1712 motorola 33 resolution doubling as discussed above can be accomplished by using these equations: where: pwmx = the value loaded into the appropriate pwm x value register pmod = the value in the pwm counter modulo register pol = 1 or C1, depending on the desired motor voltage polarity pwm = the desired pulse width (fraction between 0 and 1) these two equations have been designed to utilize the same terms to minimize the number of calculations the software needs to perform. figure 19 shows a mathcad? simulation of the equations for the condition of pmod = 20. the graph is plotted over the range 0 pwm 1. figure 19. example of resolution doubled pwms pwm1 = int pmod 2 + 0.25 + pol * pmod * pwm 2 () pwm3 = int pmod 2 + 0.25 C pol * pmod * pwm 2 () pwm fraction value pwm1 pwm2 pwmx value register pmod / 2 1.0 0 20 0
application note an1712 34 motorola encoder processing with careful software design and moderate shaft speeds, encoder signals can be decoded directly by the 'mp16 timers. in fact, motorola already is working on a software solution for this. for more demanding applications, however, external hardware is required to process the encoder signals, as shown in figure 17 . the circuitry shown decodes encoder channel information into a count clock and an up/down signal [4] . each new encoder position results in a count of the timer a counter. any change in the direction of rotation will cause an optional interrupt and a capture of the timer a value corresponding to the first encoder count in the opposite direction. since the timer a counter only counts up, the software is responsible for integrating the direction information when calculating the encoder position. figure 20 shows the timing relationships for the encoder processing circuitry. figure 20. encoder processing waveforms n+4 tch0b tch1b tch2b tch3b channel a channel b 74hc86 a output 74hc86 c output up/down 74hc86 b output timer count position captured value n n+8 n+9 n+8 n+7 n+6 n+5 n+4 n+3 n+1 n+2 0 12345678 9 1011121314151617 10 last value of direction change n+1 n+2 n+3 n+5 n+6 n+7
application note high performance servo controller an1712 motorola 35 motor velocity data is often obtained by counting encoder pulses during a given sampling period. this gives satisfactory results, assuming that the motor velocity is high enough to yield many encoder counts per sampling period. however, at slower speeds, the quantization noise becomes much more noticeable since the velocity signal is so small. indeed, one can envision the scenario of an extremely slow motor where the number of encoder counts per sampling interval is either 0 or 1. this lack of resolution often results in erratic servo behavior at slower speeds manifested by an audible "scraping" sound from the motor. to mitigate this effect, many servo systems which synthesize velocity information from the encoder will instead measure the period of the encoder signals at slower motor speeds. in fact, the slower the rotation, the higher the resolution of the period measurement. this value can then be inverted and scaled in software to obtain a velocity signal with very high resolution. the most accurate velocity information from an encoder is obtained by measuring the time between similar edges on a given signal, since the timing skew between the two encoder channels varies as a function of the encoder angle. to ensure that the velocity information is updated as frequently as possible, four timer channels are used as seen in figure 17 , resulting in an update to the velocity information every encoder count. to buffer the signals coming from the encoder, the motorola mc1489a quad line receiver is an excellent choice for several reasons related to the devices noise rejection capabilities. first, the input threshold is rated to work with ttl and cmos level signals, but will continue to function properly for input voltages up to 30 volts. also, by connecting an appropriately sized filter capacitor to the response control pin, the device provides noise spike rejection. the rejection capability increases with the capacitor size and is documented on the devices data sheet. finally, the input provides about 1 volt of hysteresis, resulting in further noise rejection.
application note an1712 36 motorola brushless dc motor controller figure 21 illustrates an example of how the 'mp16 can be used to control a brushless dc motor. by connecting the hall effect signals to the 'mp16 timer inputs, some interesting control schemes become possible. tch0b through tch2b are each programmed to perform an input capture function on any edge for the three hall sensor signals that define the commutation intervals. when an edge is detected, an interrupt is generated informing the cpu to change the waveforms to the motor. in the interrupt service routine, the rotor position is determined by examining the state of the tch0b through tch2b inputs. this is done by reading the port e data register, which reflects the state of the input pins even when they are being used by the timer. once the rotor position is determined, the 'mp16 can combine this knowledge with the desired rotation direction information and apply the appropriate motor drive signals, as illustrated in the example in figure 22 . when a transition occurs on one of the hall sensor signals, a time stamp of the event is recorded in the appropriate channel register. this information can be used to calculate accurately the speed of the motor shaft. recall that the speed of a rotating body is defined as: w (t) = d q (t) dt
application note brushless dc motor controller an1712 motorola 37 figure 21. brushless dc motor controller brushless motor pwm 1 value current processing limit v bus speed input hall a hall b hall c voltage processing value trip +5 v shunt resistor forward/reverse filtering pwm 3 pwm 5 pwm 2 pwm 4 pwm 6 atd0 fault1 atd1 fault3 pte3 atd2 hc708mp16 tch0b tch1b tch2b tch3b pwm1 pwm2 pwm3 pwm4 pwm5 pwm6
application note an1712 38 motorola figure 22. brushless dc motor commutation waveforms for forward direction [5] pwm1 pwm3 pwm5 pwm2 pwm4 pwm6 hall a hall b hall c 0 60 120 180 240 300 360 rotor electrical position (degrees)
application note brushless dc motor controller an1712 motorola 39 if the rotational speed over the previous commutation interval is assumed to be constant, then the velocity over the last commutation interval can be defined as: where: dq = the mechanical angle spanned by the last commutation interval d t = the time between the last two hall sensor signal transitions if the commutation boundaries are evenly spaced, dq is constant for that particular motor, implying that the d t measurement is sufficient for calculating velocity. once d t has been obtained, it is also possible to estimate the shaft position at any time by using this equation: where: (t) = estimated shaft position at time "t" dq = the mechanical angle spanned by the last commutation interval d t = the time between the last two hall sensor signal transitions t = the present time obtained from reading the free-running timer t cap = the captured time of the last hall sensor signal transition q tcap = the shaft position at the time of t cap (assumed to be a known value) again, the assumption is made that the motor is spinning at a constant velocity and the commutation boundaries are evenly spaced. the equation can also be solved for t in cases where a certain action must occur at a specified shaft position q (t). this value can then be placed in a timer channel to generate an output pulse or interrupt to the cpu when the estimated position is reached (channel 3 is used in figure 21 ). a useful application of this is to perform phase advancement of the commutation boundaries. due to the electrical time constant of the motor windings, it takes a certain amount of time during commutation for the field to decay in the previous winding and become established in the w = dq d t (t) = dq [t C t cap ] d t + q tcap q ? q ?
application note an1712 40 motorola new one. this delay causes a shift in the rotor angle over which the windings are energized. at slow speeds, the shift is minimal and typically is ignored. at high speeds, by the time the field becomes established in the winding, the rotor already has moved past the point where optimal torque can be developed. the result is a second order reduction in motor torque at higher speeds. to compensate for this effect, the "on-time" angles of the windings can be advanced in exactly the same way and for the same reason as a spark advance on a gasoline engine. assume that the desired commutation advance ( y ) is specified as a fraction of the commutation interval (for instance, 0 y 1). if count 1 and count 2 are the timer values corresponding to the last two hall signal transitions, the timer value corresponding to the desired commutation angle can be estimated as: count c = (count 2 C count 1 ) (1 C y ) + count 2 when the free-running timer value equals count c , the timer hardware informs the cpu that it is time to change the waveforms to the motor. hc08mp16 as a smart peripheral for motor control a few applications may require more calculating power than the cpu08 is capable of (for instance, sensorless vector control). however, the pwm module on the 'mp16 still can be used by programming the 'mp16 to act as a "smart" peripheral, as shown in figure 23 . in this case, the program in the 'mp16 has a single function, that being to parse and execute the commands sent to it from the host processor via its spi interface, which can clock data at a rate of 8 million bits per second. these commands could be anything from generating a pwm output to reporting an a/d input value. incidentally, the spi module is also useful in stand-alone applications by using it in master mode to communicate to off-chip peripherals that support the spi interface standard.
application note conclusion an1712 motorola 41 figure 23. using the 'mp16 as a smart peripheral conclusion this application note demonstrates that the hc08mp16 has the flexibility to painlessly fit into a myriad of different motor control applications. the key to its versatility is a flexible pwm module with several unique features combined with a general-purpose, low-cost cpu core. the device also has several other integrated features that were not discussed, such as a watchdog timer, a bidirectional power-on reset, a low-voltage inhibit module that generates a bidirectional reset, a reset status register that identifies the source of the last reset, and an asynchronous serial communications interface, just to name a few. add to that a full suite of development tools such as c compilers, assemblers, and development hardware, which are available today. the result is a low-cost, full-featured microcontroller that can "get your motor running" today, as well as meet the needs of tomorrow's demanding motor control applications. ac line center aligned pwms with dead-time general purpose i/o a/d inputs spi interface power converter power inverter dsp56811 hc708mp16
application note an1712 42 motorola references 1. 200-hp high-temperature superconducting motor, events in motion, motion control, may/june, 1996, pp. 6-7 2. j?nsson, ragnar, direct, indirect and natural field orientation (nfo) for control of the ac induction motor nfo drives ab, ideon, s-223 70 lund, sweden 3. brushless dc and reluctance motor drive systems, university of wisconsin, madison, course notes, august 22-24, 1994 4. mcclelland, william, tachometer circuit reduces parts count, edn design ideas special issue, vol. iii, february 16, 1989, pg. 12 5. mc33035 technical data sheet, motorola linear/interface ics device data, vol.1, rev. 4, 1993, pp. 4-57C4-78 6. wilson, d. l., ac motor control with the hc16y1 motion control development system, motorola applications paper, motorola inc., 1995 mathcad is a registered trademark of math soft.
application note notes an1712 motorola 43 notes
non-disclosure agreement required application note an1712/d ? motorola, inc., 1997 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and speci?cally disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters which may be provided in motorola data sheets and/or speci?cations can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of?cers, employees, subsidiaries, af?liates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?rmative action employer. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 1-800-441-2447 or 303-675-2140 mfax?: rmfax0@email.sps.mot.com C touchtone 602-244-6609, us & canada only 1-800-774-1848 internet: http://www.mot.com/sps/ japan: nippon motorola ltd.; tatsumi-spd-jldc, 6f seibu-butsuryu-center, 3-14-2 tatsumi koto-ku, tokyo 135, japan. 81-3-3521-8315 asia/pacific: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting kok road, tai po, n.t., hong kong. 852-26629298 mfax is a trademark of motorola, inc.

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